The present invention relates to an apparatus in a computer architecture consisting of a control processor, one or more coprocessors, and a shared data memory, and more particularly to an apparatus in such a system for permitting the control processor to continue fetching instructions from a control memory while other coprocessors are permitted access to the shared memory, and even more particularly to such an apparatus which permits the control processor to share the data memory with the coprocessors without substantially impeding the control processor's execution of a control program.
Prior art microprocessors of the type known as Von Neumann architectures have a single bus for connection to memory of all types, including Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read Only Memory (PROM), Electronically Programmable Read Only Memory (EPROM) and Electronically Erasable and re-Programmable Read Only Memory (EEPROM).
ROM, PROM and EPROM are generally used for storing program instructions because these types of memory are "non-volatile." That is, they do not lose their program contents when power is switched off. This is important for battery operated equipment that can temporarily be switched off to save battery power.
RAM and EEPROM on the other hand are used for storing temporary working variables (RAM) or data that the computer may wish to change as a result of program execution, but which must be preserved through a power-down period (EEPROM).
In the Von Neumann architecture, all of the various memory modules are coupled to the same electronic address and data bus, so that the computer is only able to access either the program memory or the data memory, but not both at once. Having one bus also means that fixed data variables can be stored in program ROM, and that program instructions can be executed from data RAM if desired.
Examples of prior art Von Neumann architectures are the INTEL 8085 and the IBM PC series microprocessors 8088, 8086, 80186, 286, 386, 486; the ZILOG Z80 and the MOTOROLA 6800, 6801, 6802, 6803 . . . 6809 and 68000 series processors.
In recognition of the use of one type of memory for program instructions and another type of memory for storing dynamically changing data, another architecture known to the prior art as the Harvard architecture is often used. The Harvard architecture is characterized by having separate buses for program memory and data memory such that program instructions cannot be executed from data memory and possibly, depending on the implementation, data cannot be written to program memory.
Both architectures, Harvard and Von Neumann, generally permit constants to be read from program memory, a mode often known as direct addressing, because there would otherwise be no means for initializing an initially empty data RAM.
Harvard architectures may permit processing speed to be increased without being impeded by the well-known memory access bottleneck phenomenon, by allowing data in RAM to be manipulated at the same time as the processor is fetching its next instruction from program ROM. This overlapping process is known as pipelining. Not all Harvard architectures employ pipelining however.
Examples of Harvard architectures are digital signal processor chips such as the Texas instruments TMS320 series and ANALOG DEVICES ADSP2100 series, which do employ pipelining.
Harvard architectures can also exist in an architecture having only a single bus for addressing and transferring data between the computer and both program and data memory types. Here, the different types of transfer (i.e., the program instructions or data) are distinguished by having separate Read, Write or Control signals for the different types of memory. These architectures cannot employ pipelining. Examples of this architecture are the INTEL 8048, 8049, 8051 series microcontrollers. Of course, the speed advantage of the Harvard architecture is sacrificed in these parts for the purpose of achieving a reduction in pin count on the integrated circuit. The advantage of separate program and data memories in this case however is that a single 16-bit address bus can address not only 65,536 bytes of data, but also 65,536 bytes of program instructions. This is in sharp contrast to a Von Neumann architecture, such as the Z80 or 8085, which has a 16-bit address bus that can only address 65,536 bytes total, which have to be split between program instructions and data, for example, 56K program and 8K data, or 32 k program and 32 k data.
Another prior art technique for speeding up the processing speed of a computer system is known as Direct Memory Access (DMA). DMA is a technique that was devised to allow peripheral devices such as disc drives, magnetic tape readers, communications modems, etc. to extract data from the computer data memory for transmission or storage in peripheral media, or conversely to place directly into computer memory data retrieved from storage devices or received by a communications modem, without significantly slowing execution of the computer which uses the same memory. This is of course only useful in so-called multiprogramming applications where there are other jobs that the computer can usefully be executing while a first job is awaiting completion of the DMA operation. DMA is an Input/Output (I/O) technique which serves as an alternative to executing computer instructions that input or output data bytes to or from memory. Thus the computer is not occupied by I/O operations, which are performed autonomously by DMA control circuits. The computer merely initializes a DMA controller to take or receive a determined number of bytes N from or into memory beginning at a determined location. The computer then suspends any task that cannot resume until the DMA operation is completed, and gets on with the next highest priority task. Upon completion of DMA, an interrupt is generated by the DMA controller in order to inform the computer that that DMA operation is complete. In response, the computer suspends the current task and resumes the task that originally requested the DMA. If the resumed task is now complete, the suspended task or a higher priority task may be resumed.
An alternative method of terminating a DMA or any I/O operation is by programming the DMA or I/O controller to detect a particular data pattern as the last in the transfer, such as an End Of File (EOF) or End Of Transfer (EOT) character.
While prior art DMA I/O techniques allow the computer to perform other tasks while awaiting I/O completion, these other tasks do not necessarily continue at the same speed of execution as in the absence of an active DMA operation, due to contention for access to the same memory. If the memory that the computer and the DMA controller may both be attempting to access is at least twice as fast as needed for a single access, it may be time-shared between alternate DMA and computer accesses such that neither experiences delay. On the other hand, if speed is limited by the memory access time, then prior art techniques require that one process or the other, either computation or I/O, be put on hold in order to allow the other process to proceed. This has the disadvantage that one cannot be absolutely sure exactly how long a given program will take to execute if DMA operations can steal RAM access cycles at arbitrary moments. In real time applications, such as controlling the timing of operations in a Time Division Multiple Access radio communication device, accurate timing is important to maintain.
It is therefore desirable to provide an improved DMA controller that allows peripheral device controllers or special purpose co-processors access to a general purpose microprocessor's data RAM in a non-contentious manner, thereby avoiding a disturbance of the program execution timing.
The connection of special purpose coprocessors together with general purpose microprocessors is also known to the prior art. Some modern digital signal processors adapted to perform fast fixed or floating point arithmetic comprise a so-called host port. A host port is a set of pin connections for attaching to a general purpose microprocessor which will orchestrate the activity of the signal processor. The nature of this host port connection however does not allow the coprocessor to directly access the microprocessor data memory, even if the host can conversely directly access the coprocessor memory. The latter is less contentious because coprocessors, including their internal memory speeds, are generally an order of magnitude faster than the general purpose host processor. Thus it is impossible for the general purpose host processor to significantly delay a fast coprocessor, but a coprocessor could on the other hand significantly delay operation of the host.
Such examples of DMA by coprocessors to host processors as exist in the prior art are of the known DMA type that allows access to memory by arbitrating between contending main processor and coprocessor demands, while the converse, of host access to coprocessor memory is achieved by cycle stealing. Thus, it is desirable to provide an apparatus which allows non-contentious access by one or more coprocessors to the host's Random Access Memory.